Adityaa Mehra
@adityaamehra
Joined on 11 November 2020
GitHub Stats
27
Followers
66
Repositories
1
Organizations
0
Gists
55
Pull Requests
0
Issues
294
Commits
0
Sponsors
6
Contributed To
10
Star Earned
Most Used Languages
96.27%
Jupyter Notebook
2.07%
Verilog
0.97%
Python
0.17%
Assembly
0.10%
HTML
0.09%
Stata
0.07%
Go
0.06%
Java
Popular Projects
RV32IM-pipelined
This is a basic 5 stage pipelined RV32IM based ISA following CPU core
Verilog
7
0
0
0
Auto-Uploader
No description
Go
1
0
0
0
CodeForces-Solution
Here are my proudly accepted solutions from the CodeForces battlefield! 🎉💻 Every bug squashed, every test case conquered—one problem at a time! 😎🔥
Java
1
0
0
0
adityaamehra
No description
Unknown
1
0
0
0
iitbhu-autologin
Auto-detects and re-logs into the IIT BHU institute firewall captive portal
Python
0
0
0
0
riscv32I-single-cycle
This is the single cycle RiscV RV32I ISA following CPU unit written in verilog.
Verilog
0
0
0
0
Top Contributions
Top contributions made by the user in the last year.
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Contributions Calendar
Contributions made by the user in the last 365 days.
Recent Activity
10/5/2026, 7:24:05 PM
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