Adityaa Mehra
@adityaamehra
Joined on 11 November 2020
As a burgeoning scholar, I am immersing myself in the vast domain of coding, with the intent to expand my knowledge and hone my expertise.
GitHub Stats
23
Followers
62
Repositories
0
Organizations
0
Gists
4
Pull Requests
0
Issues
130
Commits
0
Sponsors
0
Contributed To
10
Star Earned
Most Used Languages
96.13%
Jupyter Notebook
2.07%
Verilog
1.14%
Python
0.17%
Assembly
0.10%
HTML
0.09%
Stata
0.07%
Go
0.06%
Java
Popular Projects
RV32IM-pipelined
This is a basic 5 stage pipelined RV32IM based ISA following CPU core
Verilog
7
0
0
0
Auto-Uploader
No description
Go
1
0
0
0
CodeForces-Solution
Here are my proudly accepted solutions from the CodeForces battlefield! 🎉💻 Every bug squashed, every test case conquered—one problem at a time! 😎🔥
Java
1
0
0
0
adityaamehra
No description
Unknown
1
0
0
0
riscv32I-single-cycle
This is the single cycle RiscV RV32I ISA following CPU unit written in verilog.
Verilog
0
0
0
0
FFT-tiny-tapeout
The first succesfull tapeout from IIT(BHU)
Python
0
1
0
1
Top Contributions
Top contributions made by the user in the last year.
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Contributions Calendar
Contributions made by the user in the last 365 days.
Recent Activity
6/30/2026, 11:31:14 AM
3/24/2026, 5:48:34 PM
6/14/2026, 2:09:31 PM
6/14/2026, 2:07:49 PM
6/14/2026, 1:45:37 PM
6/11/2026, 3:05:08 PM